1. Power Electronics and Vertical U-Shaped Trench-Gated Metal-Oxide-Silicon Field-Effect Transistors Fairchild Semiconductor, Inc. Research in this area is in progress since 1999 and is conducted in collaboration with Fairchild Semiconductor, Inc. The goal is to develop and characterize a trench (~ 400 nm wide and 2.0 microns deep) structure for use in discrete power U-MOSFET device manufacturing. The focus of the research is on the following main tasks.
- Optimization of the trench etch conditions, trench side-wall cleaning, and oxide growth conditions.
- Development of models and tests allowing prediction of reliability of thick (>50 nm) gate oxides. As a part of this effort attempts are made to identify origins of fragility on the charge-to-breakdown of gate oxides in trenches. Also hot carrier stress reliability of the devices is assessed.
- Study of the damage occurring near to the drain edge of the U-MOSFET. This study is carried out using special structures that amplify the trench corner effects. More detailed transistor analysis and capacitance-voltage measurements on single and multiple U-MOSFET structures and trench capacitors are in progress.
- Investigate lower temperatures of oxidation, and thinner gate oxides (~10 nm) needed in devices for low-voltage logic and p-channel device applications.
2. Nanoelectronics and Complementary Metal-Oxide-Silicon (CMOS)/Integrated Circuit (IC) Processing: Ultra-Thin Gate Oxides and High-k Gate Dielectrics This research is concerned with the development of a gate stack system (dielectric, electrode, and their compatibility with plasma etching processes and the scaled complementary metal oxide semiconductor [CMOS] integrated circuit [IC] process flow). This issue presents major materials and processing challenges as IC industry approaches the sub-100 nm technology generation by the year 2006 and beyond. The two main research thrusts are :
- Thin gate-oxides (SiO2 of thickness below 5 nm) metal-oxide-Si (MOS) capacitor and MOS field-effect transistor (MOSFET) structures are fabricated using submicron full CMOS process flow. Damage to these structures caused by different processing steps, is studied using transistor parameter measurements, charge pumping, as well as deep-level transient spectroscopy (DLTS). Device reliability is also assessed using appropriately developed Fowler-Nordheim (FN) and hot carrier (HC) stressing protocols.
- Different high-k dielectrics, such as TiO2, SrTa2O6, ZrSiO4, and HfO2 are prepared by a variety of thin film deposition techniques. These include liquid source misted chemical deposition and chemical vapor deposition. Following deposition, detailed investigations of the electrical properties and reliabilities of these dielectrics and their interfaces with Si are carried out. As test vehicles these investigations employ metal-insulator-Si (MIS) capacitors and MISFETs devices, where the high-k dielectric is used as the gate insulator.
3. Nanoelectronics and Complementary Metal-Oxide-Silicon (CMOS)/Integrated Circuit (IC) Processing: Low-k Inter-Layer Dielectrics (ILDs) for Ultra Large-Scale Integration (ULSI) In this research area new low-k materials for ILD applications in ULSI are prepared and examined in terms of their physical and chemical properties as well as their compatibility with integrated circuit technologies. The low-k materials examined include fluorinated silicon oxides, polymers, and sculptured silicon oxides.
4. Microsensors and MEMS The ongoing research in this area is carried out in collaboration with Fairchild Semiconductors Inc. The current focus is in thermal microsensors in the form of a single p/n junction diode and arrays of several stack diodes. The properties and output of the microsensor are examined as functions of junction dimensions and scaling, temperature range, and reverse breakdown characteristics.
5. Thin-Film Transistors (TFTs) for Display and Microsensor Applications This is a study of the characteristics of polycrystalline silicon/polymer TFTs fabricated on various rigid or flexible substrates. These may be bare substrates or substrates coated with different semiconducting/insulating films. The study addresses issues regarding the performance and stability of the TFTs as function of polycrystalline silicon/polymer film preparation (deposition methods and conditions, annealing, etc.), coating material type and thickness, and substrate materials.